This invention relates to integrated circuit devices and, more particularly, to a method and a product formed thereby for matching the sensitivities of resistors to uniform manufacturing errors.
Many integrated circuit devices utilize pairs of resistors which must be deployed in critical, predetermined ratios of resistance. The proper operation of these circuits requires that these ratios fall within very narrow limits of error. While the ratios of resistance are critical, the individual values of resistance of the resistors which comprise the pairs are not critical. During the formation of these resistors, however, manufacturing processes result in a uniform, systematic error in the cutting or etching of the edges of the sections produced. This systematic error varies in magnitude from batch to batch of manufactured resistors, but is uniform within any one group. Since the etching error is always uniform within any one process group, paris of resistors can be deployed in predetermined ratios that will remain constant even after processing introduces the etching error. The design constraint of requiring highly accurate, predetermined ratios is thereby satisfied, although the cutting error causes the absolute values of the individual resistors in the pair to vary disproportionally.
A more general way of looking at the problem is to observe that various manufacturing steps affect the edges of resistors on any given chip in a uniform manner. If the resistors are over-etched, for example, each resistor will turn out to be less than the desired width by almost the same incremental amount. Since this amount depends very little on the design width of the resistor, it will affect different-sized resistors in different proportions. The resistance of wide resistors will be affected only a little, while that of narrow ones will be affected a great deal by the same fixed error in width.
Different-sized resistors sections, then, experience different relative changes in resistance due to this edge error. Given two rectangular sections of equal fixed lengths and widths W and 2W, an etching error, e, which affects each pair of edges would change the resistance of the section having width W twice as much as the resistance of the section having width 2W. The smaller of these two resistor sections is twice as sensitive to changes in resistance due to changes in width. For example, given one resistor 5 mils wide and another 10 mils wide, an etching error which causes a variation of width of 0.03 mil on each edge would result in changes in total resistance of (0.03.times.2)/5=1.2% and (0.03.times.2)/10=0.6% respectively.
Various methods can be used to circumvent this problem. For example, in the case of R-2R networks, resistors of one size only are often employed by joining two such resistors in series to form the 2R branches of this circuit. Uniform edge related errors may affect the total resistance of this network, but will not affect the critical R-2R ratio. Other special cases have particular solutions such as the use of numbers of identical resistors segments to form integral ratios other than two. When large or non-integral ratios are involved, however, fields of interconnected identical resistors become impractical.
An object of the present invention is to provide a method for equalizing or matching the sensitivities of different-sized resistors to relative changes in resistance resulting from changes in width. This method is useful in the process of manufacturing pairs of resistors which must have predetermined ratios of resistance within strict error limits. This ratio of resistance must be held at a predetermined constant despite the manufacturing error described above which introduces variations in width along each edge of the resistors and also changes the resistance of the resistors. Changes in the resistance of each resistor in the pair are acceptable so long as the ratio of the two resistance values remains constant after manufacture is completed.